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indus t r y a nd mul ti ma rk et high - p erf or manc e dr m o s 6 mm x 6 mm x 0.8 mm iqfn dat a she et revision 1.9 , 2011 - 03 - 31 preliminary td a21 220
edition 2011 - 03 - 31 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be r egarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non - infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please co ntact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the n earest infineon technologies office. infineon technologies components may be used in life - support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the fa ilure of that life - support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human lif e. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TDA21220 preliminary data sheet 3 revision 1.9 , 2011 - 03 - 31 revision history page or item su bjects (major changes since previous revision) revision 1.9 , 2011 - 03 - 31 all update format of document. table 6 define the ac values. figure 1 update the package picture table 14 correct a typo on logic function of smod pin figure 9 clarify the definition o f t_ghtsshd and t_gltsshd table 11 up date the toff_min_pwm to min 65 ns trademarks of infineon technologies ag aurix?, bluemoon?, c166?, canpak?, cipos?, cipurse?, comneon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econodual?, econopim?, eicedriver?, eup ec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my - d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pro - sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smar tlewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x - gold?, x - pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent technologies, amba?, arm?, multi - ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat - iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporati on. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektronix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vly nq? of texas instruments incorporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited . last trademarks update 2010 - 10 - 26
TDA21220 applications preliminary data sheet 4 revision 1.9 , 2011 - 03 - 31 1 applications ? desktop and server vr11.x and vr12 vcore and non - vcore buck - converter ? network and tel ecom processor vr ? single phase and multiphase pol ? cpu/gpu regulation in notebook, desktop graphics cards, ddr memory, graphic memory ? high power density voltage regulator modules (vrm). 2 features ? compliant to intel ? vr1 2 driver and mosfets module (drmos) fo r desktop/server applications ? for synchronous buck step down voltage applications ? maximum average current of 50 a ? input voltage range +4.5 v to +16 v ? power mosfets rated 25 v for safe operation under all conditions ? extremely fast switching technology for i mproved performance at high switching frequencies (> 1 mhz) ? remote driver disable function ? switch modulation (smod#) of low side mosfet ? includes bootstrap diode ? shoot through protection ? +5 v high and low side driving voltage ? compatible to standard +3.3 v p wm controller integrated circuits ? three - state pwm input functionality ? small package: iqfn40 (6 x 6 x 0.8 mm3) ? rohs compliant table 1 product identification part number temp range package marking TDA21220 - 25 to 125 ? figure 1 picture of the product
TDA21220 description preliminary data sheet 5 revision 1.9 , 2011 - 03 - 31 3 description 3.1 pinout figure 2 pinout, numbering and name of pins (transparent top view) note: signals marked with # at the end are active low signals. table 2 i/o signals pin no. name pin type buffer type function 1 smod# i +3.3 v logic high and low side gate disable when smod# is low the gl is off 6 gh o analog high side gate signal monitoring of high side mosfet gate 7 phase o analog switch node output internally connected to vswh pin, connect to boot capacitor 4 boot i analog bootstrap volta ge pin connect to boot capacitor 15, 29 to 35, vswh pad vswh o analog switch node output high current output switching node 36 gl o analog low side gate signal monitoring of low side mosfet gate 39 disb# i +3.3 v logic disable signal (active low) pull t o gnd to disable the ic. 40 pwm i +3.3 v logic pwm drive logic input the three state pwm input is compatible with 3.3 v. vswh vin 1 2 3 4 5 6 7 8 9 10 11 40 20 21 31 30 cgnd vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd pwm vswh vswh vswh vswh vswh gl cgnd nc disb# pwm vswh vswh vswh vswh vswh gl cgnd nc disb# 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 39 38 37 36 35 34 33 32 vin vin nc phase gh cgnd boot vdrv vcin smod# vin vin nc phase gh cgnd boot vdrv vcin smod# pgnd pgnd pgnd vswh vswh pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd vswh vswh pgnd pgnd pgnd pgnd pgnd
TDA21220 description preliminary data sheet 6 revision 1.9 , 2011 - 03 - 31 table 3 power supply pin no. name pin type buffer type function 2 vcin power C logic supply voltage 5 v bias voltage for the internal logic 3 vdrv power C fet gate supply voltage high and low side gate drive 5 v supply 9 to 14, vin pad vin power C input voltage supply of the drain of the high side mosfet table 4 ground pins pin no. name pin type buffer type function 5, 37, cgnd pad cgnd gnd C co ntrol signal ground should be connected to pgnd externally 16 to 28 pgnd gnd C power ground all these pins must be connected to the power gnd plane through multiple low inductance vias. table 5 not connected pin no. name pin type buffer type function 8, 38 nc C C no internal connection leave pin floating or tie to gnd.
TDA21220 description preliminary data sheet 7 revision 1.9 , 2011 - 03 - 31 3.2 general description the infineon TDA21220 is a multichip module that incorporates infineons premier mosfet technology for a single high side and a single low side mosfet coupled with a robust, h igh performance, high switching frequency gate driver in a single 40 pin qfn package. the optimized gate timing allows for significant light load efficiency improvements over discrete solutions. state of the art mosfet technology provides exceptional full load performance. thus this device has a clear advantage over existing approaches in the marketplace when both full load and light load efficiencies are important. when combined with the infineons primarion? controller family of digital multi - phase contro llers, the TDA21220 forms a complete core - voltage regulator solution for advanced micro and graphics processors as well as point - of - load applications. the TDA21220 is pin to pin compatible and compliant with the intel 6x6 drmos specification. the device pa ckage height is only 0.8 mm, and is an excellent choice for applications with critical height limitations. figure 3 simplified block diagram s m o d # d i s b # p g n d v s w h h s d r i v e r l s d r i v e r l e v e l s h i f t e r u v l o h s l o g i c l s l o g i c i n p u t l o g i c 3 - s t a t e p w m v c i n v d r v c g n d g l b o o t v i n i c d r i v e r p h a s e l s m o s h s m o s s h o o t t h r o u g h p r o t e c t i o n v d r v 5 0 0 k c g n d 7 k 1 c g n d 1 6 k 5 v c i n 6 0 0 k c g n d 4 0 0 k v c i n v d r v 5 0 0 k 5 0 0 k d i s b # p g n d v s w h h s d r i v e r l s d r i v e r l e v e l s h i f t e r u v l o h s l o g i c l s l o g i c i n p u t l o g i c 3 - s t a t e p w m v c i n v d r v c g n d g l b o o t g h v i n i c d r i v e r p h a s e l s m o s h s m o s s h o o t t h r o u g h p r o t e c t i o n v d r v 5 0 0 k c g n d 7 k 1 c g n d 1 6 k 5 v c i n 6 0 0 k c g n d 4 0 0 k v c i n v d r v 5 0 0 k 5 0 0 k
TDA21220 electrical specification preliminary data sheet 8 revision 1.9 , 2011 - 03 - 31 4 electrical s pecification 4.1 absolute maximum ratings note: t a = 25c stresses above those listed in table 6 absolute maximum ratings may cause permanent damage to the device. these are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in the operational sect ions of this specification. exposure to the absolute maximum ratings for extended periods may adversely affect the operation and reliability of the device. table 6 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. f requency of the pwm input f sw C C C i out C C C v in (dc) - 0.30 C C v cin (dc) - 0.30 C C v drv (dc) - 0.30 C C v swh (dc) - 1 C C v swh (ac) - 10 1 C C v phase (dc) - 1 C C v phase (ac) - 10 C C v boot (dc) - 0.3 C C v boot (ac) - 1 1 C C v boot - phase (dc) - 1 C C v smod# (dc) - 0.3 C C v disb 2 - 0.3 C C v pw m 2 - 0.3 C C t jmax - 40 C ? C t stg - 5 5 C ? C note: all rated voltages are relative to voltages on the cgnd and pgnd pins unless otherwise specified. 1 ac is limited to 10 ns 2 latch up class ii - level b (jedec 78). please refer to quality report for details.
TDA21220 electrical specification preliminary data sheet 9 revision 1.9 , 2011 - 03 - 31 4.2 thermal characteristics table 7 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance, junction - solderin g point 1 js C 5 C k/w C thermal resistance, junction - top of package jtop C 20 C C 4.3 recommended operating conditions and electrical characteristics note: v drv = v cin = 5 v, t a t = 25c table 8 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. input voltage v in 5 C 16 v C mosfet driver voltage v drv 4.5 5 6 C logic supply voltage v cin 4.5 5 6 C junction temperature t jop - 25 C +125 c C table 9 voltage supply and biasing current parameter symbol values unit note / te st condition min. typ. max. driver current i vdrv_300khz C C f sw = 300 khz i vdrv_pwml C C a i vcin_pwml C C i vcin_o C C i cin + i drv C C v uvlo_r 2.9 3.5 3.9 v vcin rising uvl o falling v uvlo_f 2.5 3.1 3.3 vcin falling 1 the junction - soldering point is referred to the vswh bottom exposed pad.
TDA21220 electrical specification preliminary data sheet 10 revision 1.9 , 2011 - 03 - 31 table 10 logic inputs and threshold parameter symbol values unit note / test condition min. typ. max. disb# input low v disb_l 0.7 1.1 1.3 v v disb falling input high v disb_h 1.9 2.1 2.4 v disb rising sink curr ent i disb C C a v disb = 1 v smod# input low v smod#_l 0.7 1.1 1.3 v v smod# falling input high v smod#_h 1.9 2.1 2.4 v smod# rising open voltage v smod#_o C C C i smod# C C a v smod# = 1 v pwm input low v pwm_l C C v pwm falling input high v pwm_h 2.4 C C v pwm rising input resistance r in - pwm 3 5 7 k ? v pwm = 1 v open voltage v pwm_o C C v pwm_o tristate shutdown window 1 v pwm_s 1.2 C C table 11 timing characteristics parameter symbol values unit note / test condition min. typ. ma x. three state to gl/gh rising delay t_pts C C C C C C C C C C C C C C C C C C C C C C 1 maximum voltage range for tri - state
TDA21220 theory of operation preliminary data sheet 11 revision 1.9 , 2011 - 03 - 31 5 theory of operation the TDA21220 incorporates a high performance gate driver, one high - side power mosfet and one low - side power mosfet in a single 40 lead qfn package. the advantages of this a rrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.this module is ideal for use in synchronous buck regulators either as a stand - alone power stage that can deliver up to 50 a or with an interleaved approach for higher current loads. the power mosfets are tailored for this device. the gate driver is a robust high - performance driver rated at the switching node for dc voltages ranging from - 1 v to +25 v. the closely coupled driver an d mosfets enable efficiency improvements that are hard to match using discret e components. the power density for transmitted power of this approach is approximately 4 0 w within a 36 mm 2 area. 5.1 driver characteristics the gate driver of the TDA21220 has 2 vol tage inputs, vcin and vdrv. vcin is the 5 v logic supply for the driver. vdrv is also 5 v and is used to drive the high and low side mosfets. ceramic capacitors should be placed very close to these input voltage pins to decouple the sensitive control circu itry from a noisy environment. the mosfets selected for this application are optimized for 5 v gate drive, thus giving the end user optimized high load as well as light load efficiency. the reference for the power circuitry including the driver output stag e is pgnd and the reference for the gate driver control circuit (vcin) is cgnd. referring to the block diagram page, vcin is internally connected to the uvlo circuit and for vcin voltages less than required for proper circuit operation will provide shut - do wn. vdrv supplies both, the floating high side drive and the low - side drive circuits. an active boot circuit for the high side gate drive is also included. a second uvlo circuitry, sensing the boot voltage level, is implemented to prevent false gh turn on during insufficient power supply level condition (boot cap charging/discharging sequence). during undervoltage both gh and gl are driven low actively; further passive pull - down ( 50 0 k ? ) is placed across gate - source of both fets . figure 4 internal output signal from uvlo unit v cin h l uvlo_f v uvlo_r uvlo output log ic level shutdown enable
TDA21220 theory of operation preliminary data sheet 12 revision 1.9 , 2011 - 03 - 31 5.2 inputs to the internal control circuits the pwm is the control input to the ic from an external pwm controller and is compatible with 3.3 v. the pwm input has three - state functionality. when the voltage remains in the specified pwm - shutdown - window for at least the pwm - shutdown - holdoff time t_tsshd , the operation will be suspended by keeping both mosfet gate outputs low. once left open, the pin is internally fixed to v pwm_o = 1.5 v level . table 12 pwm pin functionality pwm logic level driver output low gl= high, gh = low high gl = low, gh = high open (left floating, or high impedance) gl = low, gh = low the possibility to use a wide range of vcin power supply voltages (from 4.5 v to 5.5 v) implies a shifting in the thr eshold voltages for the following parameters: v pmw_o , v pwm_h , v pwm_l . the typical behavior of these thresholds with the vcin power supply is shown in the following graph: figure 5 variation of pwm levels versus vcin logic supply volta ge attention: the vpwm_s also scales in the same way. the disb# is an active low signal. when disb# is pulled low, the power stage is disabled. the disable pin is pulled down also during the thermal shut down condition.
TDA21220 theory of operation preliminary data sheet 13 revision 1.9 , 2011 - 03 - 31 table 13 disb# pin functionality disb# logic level driv er output low shutdown : gl = gh = low high enable : gl = gh = active open (left floating, or high impedance) shutdown : gl = gh = low the smod# fea ture is provided to disable the low side s mosfet during active operation. when synchronized with the pwm signal, smod# i ntended to improve light load efficiency by sav ing the gate charge loss of the low - side mosfet. once left open, the pin is internally fixed to v smod# _o =3 v level. table 14 smod# pin functionality smod# logic level driver output low shutdown : gl = low gh = pwm high enable : gl = gh = active open (left floating, or high impedance) enable : gl = gh = active 5.3 shoot through protection the TDA21220 driver includes gate drive functionality to protect against shoot through. in order to protect the p owe r stage from overlap, both high side and l ow s ide mosfets being on at the same time, the adaptive control circuitry monitors the voltage at the vswh pin. when the pwm signal goes low, the high s ide mosfet will begin to turn off, after the propagation del a y (t_pdlu). once the vswh pin falls b elow 1 v, the low s ide mosfet is gated on after the predefined delay time, (t_pdhl). additionally, the gate to source voltage of the high side mosfet is also monitored. when vgs(h igh s ide ) is discharged below 1 v, a threshold known to turn h igh s ide mosfet off, a secondary delay is initiated, (t_pdhl), which results in l ow s ide being gated on irregardless of the state of the vswh pin.this way it will be ensured that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each swi tching cycle. see figure 9 for more detail. gh and gl are monitoring pins to check the internal gate drive signals. 5.4 safe operating area the maximum load cur rent versus the temperature of the pcb (below the device) is given below: figure 6 safe operating area 0 10 20 30 40 50 60 0 25 50 75 100 125 150 iload max (a) pcb temperature ( c) safe operating area iload
TDA21220 application preliminary data sheet 14 revision 1.9 , 2011 - 03 - 31 6 application 6.1 implementation figure 7 pin interconnection outline (transparent top view) note: 1. pin phase is internally connected to vswh node 2. it is recommended to place a rc filter between vcin and vdrv as shown. 3. during power - up and down sequences, the pwm signal must be either low or tri - state (open voltage), but never high, in order to avoid uncontrolled output voltage. v s w h v i n 1 2 3 4 5 6 7 8 9 1 0 1 1 4 0 2 0 2 1 3 1 3 0 c g n d v i n v s w h p g n d p w m v s w h g l n c d i s b # 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 v i n n c p h a s e g h c g n d b o o t v d r v v c i n s m o d v s w h p g n d 1 u f c i n v i n ( + 5 - 2 0 v ) c b o o t + 5 v s i g n a l g n d p o w e r g n d v o u t l 1 u f c g n d v s w h v i n 1 2 3 4 5 6 7 8 9 1 0 1 1 4 0 2 0 2 1 3 1 3 0 c g n d v i n v s w h p g n d p w m v s w h g l c g n d n c d i s b # 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 v i n n c p h a s e g h c g n d b o o t v d r v v c i n s m o d v s w h p g n d 1 u f 2 x 2 2 u f 2 x 1 u f 1 x 0 . 1 u f c i n v i n ( + 5 2 0 v ) c b o o t s i g n a l g n d p o w e r g n d v o u t l 1 u f 1
TDA21220 application preliminary data sheet 15 revision 1.9 , 2011 - 03 - 31 6.2 typical application figure 8 four phases voltage regulat or typical application (simplified schematic) v i n ( + 1 2 v ) v o u t v d r v ( + 5 v ) r b l c b 1 ? c b o o t d r m o s v i n v s w h b o o t p g n d v d r v v c i n p w m p h a s e c g n d d i s b # s m o d # r b l c b 1 ? c b o o t d r m o s v i n v s w h b o o t p g n d v d r v v c i n p w m p h a s e c g n d d i s b # s m o d # r b l c b 1 ? c b o o t d r m o s v i n v s w h b o o t p g n d v d r v v c i n p w m p h a s e c g n d d i s b # s m o d # r b l c b 1 ? c b o o t d r m o s v i n v s w h b o o t p g n d v d r v v c i n p w m p h a s e c g n d d i s b # s m o d # + 3 . 3 v c e x t _ m i 2 c i n t e r f a c e s v i d i n t e r f a c e p x 3 8 9 5 p w m 1 i s e n 1 n i s e n 1 p p w m 2 i s e n 2 n i s e n 2 p p w m 3 i s e n 3 n i s e n 3 p p w m 4 i s e n 4 n i s e n 4 p v s e n n t s e n v d d v r _ e n v r _ r e a d y s d a s c l s a d d r _ m v s e n p s a d d r _ l b v r _ r e a d y v d i o v c l k v a d d r f a u l t 1 k ? r e x t _ m
TDA21220 gate driver timing diagram preliminary data sheet 16 revision 1.9 , 2011 - 03 - 31 7 gate driver timing diagram figure 9 adaptive gate driver timing diagram pwm gl gh 1 v 1 v three_state v pwm_l t_pdhl t_ gl tsshd t_pdll t_pdhu t_pdlu v pwm_h v pwm_h v pwm_l t_ gh tsshd t_pts t_pts vswh note : vswh during entering/exit to tri - state behaves accordingly to inductor current.
TDA21220 gate driver timing diagram preliminary data sheet 17 revision 1.9 , 2011 - 03 - 31 figure 10 disb# timing diagram figure 11 smod# timing diagram disbl# gh/gl t_pdl(disb) v disb_l t_pdh(di sb) v disb_h v s w h p w m g l d c m c c m c c m s m o d d i s a b l e d s m o d p w m g l s m o d a c t i v e d c m c c m c c m s m o d t _ p d l u s m o d d i s a b l e d
TDA21220 performance curves C typical data preliminary data sheet 18 revision 1.9 , 2011 - 03 - 31 8 performance curves C typical data 8.1 eff iciency and power loss versus vout operating conditions (un less otherwise specified): vin = +12 v, vcin = vdrv = +5 v, vout = 0.8 v to 1.6 v, f sw = 362 khz, 210 nh inductor (c ooper - fpi1108, dcr (typ) = 0.29 m ) ta = 25 c, load line = 0 m, airflow = 100 lfm, no heatsink. efficiency and power loss reported herein includes only TDA21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 12 efficie ncy vs. vout 76 78 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 30 35 40 45 50 efficiency (%) output load current (a) vout_362khz_12v_0.8v vout_362khz_12v_1v vin_362khz_12v_1.2v vout_362khz_12v_1.35v vout_362khz_12v_1.6v
TDA21220 performance curves C typical data preliminary data sheet 19 revision 1.9 , 2011 - 03 - 31 figure 13 power loss vs. vout 8.2 efficiency and power loss versus vin operating conditions (unless otherwise specified): vin = +10/12/14 v, vcin = vdrv = +5 v, vout = 1.2 v, f sw = 362 khz, 210 nh inductor (cooper - fpi1108, dcr (typ) = 0.29 m ) ta = 25 c, load line = 0 m, airflow = 100lfm, no heatsink. efficiency and power loss reported herein includes only TDA21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. 0 2 4 6 8 10 12 14 0 5 10 15 20 25 30 35 40 45 50 power loss (w) output load current (a) vout_362khz_12v_0.8v vout_362khz_12v_1v vout_362khz_12v_1.2v vout_362khz_12v_1.35v vout_362khz_12v_1.6v
TDA21220 performance curves C typical data preliminary data sheet 20 revision 1.9 , 2011 - 03 - 31 figure 14 efficiency vs. vi n figure 15 power loss vs. vin 76 78 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 30 35 40 45 50 efficiency (%) output load current (a) vin_362khz_10v_1.2v vin_362khz_12v_1.2v vin_362khz_14v_1.2v 0 2 4 6 8 10 12 0 5 10 15 20 25 30 35 40 45 50 power loss (w) output load current (a) vin_362khz_10v_1.2v vin_362khz_12v_1.2v vin_362khz_14v_1.2v
TDA21220 performance curves C typical data preliminary data sheet 21 revision 1.9 , 2011 - 03 - 31 8.3 efficiency and power loss versus switching frequency operating conditions (unless otherwise specified): vin= +12 v, vcin=vdrv= +5 v, vout=1.2 v, fsw = 296 khz to f sw = 592 khz, 210 nh inductor (cooper - fpi1108, dcr (typ) =0.29 m ) t a = 25 c, load line = 0 m , airflow = 100 lfm, no heatsink. efficiency and power loss reported herein includes only TDA21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 16 efficiency vs. fsw 76 78 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 30 35 40 45 50 efficiency (%) output load current (a) freq_296khz_12v_1.2v freq_362khz_12v_1.2v freq_407khz_12v_1.2v freq_465khz_12v_1.2v freq_592khz_12v_1.2v
TDA21220 performance curves C typical data preliminary data sheet 22 revision 1.9 , 2011 - 03 - 31 figure 17 power loss vs. fsw 0 2 4 6 8 10 12 14 0 5 10 15 20 25 30 35 40 45 50 power loss (w) output load current (a) freq_296khz_12v_1.2v freq_362khz_12v_1.2v freq_407khz_12v_1.2v freq_465khz_12v_1.2v freq_592khz_12v_1.2v
TDA21220 performance curves C typical data preliminary data sheet 23 revision 1.9 , 2011 - 03 - 31 8.4 driver current versus switching frequency operating conditions (unless otherwise specified): vin= +12 v, vcin=vdrv= +5v, vout =1.2 v, from f sw = 296 khz to f sw = 592 khz, 210 nh indu ctor (cooper - fpi1108, dcr (typ) = 0.29 m ) ta = 25 c, load line = 0 m, airflow = 100 lfm, no heatsink. efficiency and power loss reported herein includes only TDA21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 18 idr vs fsw 0 0.005 0.01 0.015 0.02 0.025 296 362 407 465 592 idr vs fsw
TDA21220 mechanical drawing preliminary data sheet 24 revision 1.9 , 2011 - 03 - 31 9 mechanical drawing figure 19 mechanical dimensions
TDA21220 mechanical drawing preliminary data sheet 25 revision 1.9 , 2011 - 03 - 31 figure 20 footprint and solder stencil recommendations
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